The invention relates to a circuit arrangement with a protective arrangement at least partially integrated into it and protecting the integrated circuit arrangement from high-energy electrical faults acting upon it.
High-energy electrical faults are, for example, faults resulting from electrostatic discharges and that can affect the connections of integrated circuits when the latter are handled and so cause irreversible changes in the integrated circuit and even render it useless. Electrostatic discharges of this nature occur in a variety of types and intensities and are therefore difficult to describe in detail. However, in order to gauge the sensitivity of integrated circuits to such faults with a finite probability, integrated circuits too --and electronic components in general --are increasingly being subjected to stress tests that simulate electrostatic discharge processes by means of certain test arrays. In these tests, the connections of the integrated circuit are subjected to a certain pulse-type load in accordance with a specified pattern.
In principle, a capacitor of given capacitance is charged to a specified voltage in stress tests, and discharged under certain conditions via the component being tested. In practice, two versions of test circuits are preferred, and are described in greater detail in the following. The first version of a test circuit is shown in FIG. 1. In the test circuit according to FIG. 1, the capacitor C is charged from a voltage source Q via the resistor R1 and discharged via resistor R2 and the test object by operating the switch S. The resistor R2 is here only intended to protect the voltage source Q and to avoid dangerous ground faults in case of contact.
The second version of a test circuit is shown in FIG. 4. The test circuit in FIG. 4 differs from the circuit shown in FIG. 1 in that the resistance R2 of the first version has been dispensed with. The omission of resistor R2 in the second version has the effect that the full electrical energy of the charged capacitor C acts on the test object in the second test circuit version (FIG. 4). The first version of the test circuit is used mainly for testing MOS circuits, while the second version is increasingly being used for testing bipolar integrated circuits. The appropriate test specifications state that the tests must be conducted with both polarities.
The stress tests carried out on integrated circuits have shown that the appearance of damaged circuit elements largely corresponds to that obtained in practice, so that the described testing methods can be applied more and more for the assessment of integrated circuits. Moreover, test methods of this type will be used for evaluation of the protective arrangement in the development of these protective arrangements for integrated circuits.
In order to obtain a clear picture of the processes that take place during testing using the known test circuits (version 1 or version 2), the discharge processes taking place were simulated, as these processes are not measurable in practice because of their non-periodical and rapid nature. For this purpose, the test circuit first had to be converted to an equivalent circuit suitable for simulation. FIG. 2 shows the equivalent circuit used for simulation of the test circuit according to FIG. 1 (version 1). In the simulation, the test object was first replaced by an ohmic load resistor R.sub.L. The load resistor R.sub.L was first set at 1 Ohm. In the equivalent circuit according to FIG. 2, the changeover process of the switch S is simulated by a voltage jump of the generator Q. The important circuit elements of the discharge circuit are, according to FIG. 2, represented by the elements C, L1, R3, C1, L2, R4, C2, R5, C3, R6 and R.sub.L.
The self-inductance L1 of the equivalent circuit according to FIG. 2 characterizes the connected self-inductance of the capacitor C of FIG. 1. The resistor R3 characterizes the transition resistances of switch S, and capacitor C1 represents the capacitance of switch S in the switch setting K1 and the power cable capacitances to resistor R2. Resistor R2 is simulated by the elements L2, R4, R5, C3 and R6. The load is simulated by the resistor R.sub.L.
FIG. 3 shows the result of the simulation based on the equivalent circuit according to FIG. 2. In the simulation the voltage generator Q was switched from zero to 2000 V (positive). FIG. 3 shows the current curve as a function of time when an ohmic resistance R.sub.L =1 Ohm is used for load simulation. The current shown in FIG. 3 is the current flowing through the load resistor.
FIG. 5 shows the equivalent circuit for the test circuit according to FIG. 4. The inductance L3 characterizes the self-inductance of the discharge circuit of FIG. 4, while the resistor R7 characterizes the self-damping of the discharge circuit of FIG. 4. The load is simulated by R.sub.L.
FIG. 6 shows the result of the simulation with the aid of the equivalent circuit according to FIG. 5, for a voltage jump in the generator Q at zero time from zero to 500 V. R.sub.L has the value of 1 Ohm here also. As in FIG. 3, the simulated time range + (abscissa) extends from 0 to 100 nsecs.
If FIGS. 3 and 6 are compared, it can be seen that when the second test circuit (FIG. 4) is used, considerably higher currents are encountered than with the use of the first test circuit (FIG. 1). This result applies for both polarities of the generator voltage. It must be taken into account here that the voltage of the generator Q that was used in the second test method is substantially lower than the voltage used in the first test method, i.e. 500 V compared with 2000 V in the first test method.
From this comparison it is clear that the second test method is (or appears to be) substantially more critical for the integrated circuit being tested than the first test method.
In addition to the current/time curve, the output/time curve is also of interest. FIG. 7 shows the output/time curve for load resistor R.sub.L when R.sub.L =1 Ohm. The output/time curve of FIG. 7 is also obtained by simulation, in particular by forming the product of voltage and current at resistor R.sub.L. The current/time curve was determined using the equivalent circuit according to FIG. 4. This also applies for FIGS. 8 and 9, of which FIG. 8 shows the current/time curve for a load resistor R.sub.L =11 Ohm and FIG. 9 the output/time curve also for a load resistor R.sub.L =11 Ohm. Accordingly, a higher value for R.sub.L implies the occurrence of a substantially higher peak output value with more rapid decrease at the same time. The illustrations show that the short-term load is substantially greater the higher the load resistance in the value range illustrated.
Tests have shown that integrated circuits subjected to the tests described frequently have local "melt channels" in the area of the circuit components under load, these being due to severe local overheating. Occurrences of this nature can be frequently found in the semiconductor zones with weak doping. It is therefore probable that the "melt channels" result from a temperature-induced intrinsic conduction (an increase in resistance with a rise in temperature) of the semiconductor material, said conduction exceeding the extrinsic conduction as the material exceeds certain temperatures. Since the intrinsic conduction (inversion density) rises exponentially with the temperature, the current concentrates cumulatively in a "kindled" semiconductor area of this type and so heats up the semiconductor material locally. This process is not generally controllable; this is understandable when, as the theory on the temperature dependence of intrinsic conduction (inversion density) for silicon states, the intrinsic conduction is decisive for the electrical resistance in a silicon zone with an impurity concentration of, for example, 10.sup.15 cm .sup.-3 at a temperature of only approx. 280.degree. C., i.e. the conductivity rises exponentially from a crystal temperature of this value. By way of comparison this is only the case above approx. 1400.degree. C. with an impurity concentration of 10.sup.19 cm .sup. -3, i.e. at temperatures close to the melting point of silicon.